1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device having memory cells, of which passing current changes depending on storage data during access.
2. Description of the Background Art
In semiconductor memory devices for executing data storage, various forms have been employed for storing data in memory cells. For example, a semiconductor memory device is configured such that a current passing through each memory cell changes depending on storage data during access. In this semiconductor memory device, storage data is read out from a selected memory cell (i.e., access target) in accordance with results of a comparison between the passing current of the selected memory cell and a preset reference current during the access. As a kind of semiconductor memory device having such memory cells, attention is being given to an MRAM (Magnetic Random Access Memory) device, which can nonvolatilely store data with low power consumption.
Particularly, in recent years, it has been announced that a performance of the MRAM device can be dramatically improved by using the thin film magnetic members, which utilize the MTJs (magnetic tunneling junctions), as memory cells. The MRAM device with memory cells having the magnetic tunneling junctions has been disclosed in technical references such as xe2x80x9cA 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in Each Cellxe2x80x9d, ISSCC Digest of Technical Papers, TA7.2, February 2000, xe2x80x9cNonvolatile RAM based on Magnetic Tunnel Junction Elementsxe2x80x9d, ISSCC Digest of Technical Papers, TA7.3, February 2000.
FIG. 16 conceptually shows a structure of a memory cell, which has a magnetic tunneling junction, and may be merely referred to as an xe2x80x9cMTJ memory cellxe2x80x9d hereinafter.
Referring to FIG. 16, a MTJ memory cell includes a tunneling magneto-resistance element TMR having an electric resistance, which is variable in accordance with a data level of magnetically written storage data, and an access transistor ATR. Access transistor ATR is located between a write bit line WBL and a read bit line RBL, and is connected in series to tunneling magneto-resistance element TMR. Typically, access transistor ATR is formed of a field-effect transistor arranged on a semiconductor substrate.
For the MTJ memory cell, the device includes write bit line WBL and a write digit line WDL for carrying a data write current in different directions during a data write operation, respectively, a word line WL for instructing data reading, and read bit line RBL for receiving a data read current. In the data read operation, tunneling magneto-resistance element TMR is electrically coupled between write bit line WBL carrying a ground voltage GND and read bit line RBL in response to turn-on of access transistor ATR.
FIG. 17 conceptually shows an operation of writing data in the MTJ memory cell.
Referring to FIG. 17, tunneling magneto-resistance element TMR has a ferromagnetic material layer, which has a fixed and uniform magnetization direction, and may be merely referred to as a xe2x80x9cfixed magnetic layerxe2x80x9d hereinafter, and a ferromagnetic material layer VL, which is magnetized in a direction depending on an externally applied magnetic field, and may be merely referred to as a xe2x80x9cfree magnetic layerxe2x80x9d hereinafter. A tunneling barrier (tunneling film) TB formed of an insulator film is disposed between fixed magnetic layer FL and free magnetic layer VL. Free magnetic layer VL is magnetized in the same direction as fixed magnetic layer FL or in the opposite direction in accordance with the level of the storage data to be written. Fixed magnetic layer FL, tunneling barrier TB and free magnetic layer VL form a magnetic tunneling junction.
Tunneling magneto-resistance element TMR has an electric resistance, which is variable depending on a correlation in magnetization direction between fixed magnetic layer FL and free magnetic layer VL. More specifically, the electric resistance value of tunneling magneto-resistance element TMR takes a minimum value Rmin when the magnetization directions of fixed magnetic layer FL and free magnetic layer VL are same (parallel) to each other. When the magnetization directions of them are opposite (untiparallel) to each other, the above electric resistance value takes a maximum value Rmax.
In the data write operation, word line WL is inactive, and access transistor ATR is off. In this state, the data write currents for magnetizing free magnetic layer VL are supplied to bit line BL and write digit line WDL in directions depending on the level of write data, respectively.
FIG. 18 conceptually shows a relationship between the data write current and the magnetization direction of the tunneling magneto-resistance element in the data write operation.
Referring to FIG. 18, an abscissa gives a magnetic field, which is applied along an easy axis (EA) to free magnetic layer VL of tunneling magneto-resistance element TMR. An ordinate H(HA) indicates a magnetic field acting along a hard axis (HA) on free magnetic layer VL. Magnetic fields H(EA) and H(HA) correspond to two magnetic fields produced by currents flowing through bit line BL and write digit line WDL, respectively.
In the MTJ memory cell, the fixed magnetization direction of fixed magnetic layer FL is parallel to the easy axis of free magnetic layer VL, and free magnetic layer VL is magnetized in the magnetization easy direction, and particularly in the same parallel direction, which is the same direction as fixed magnetic layer FL, or in the opposite parallel direction, which is opposite to the above direction, depending on the level (xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d) of the storage data. The MTJ memory cell can selectively store data (xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d) of one bit corresponding to the two magnetization directions of free magnetic layer VL.
The magnetization direction of free magnetic layer VL can be rewritten only when a sum of applied magnetic fields H(EA) and H(HA) falls within a region outside an asteroid characteristic line shown in FIG. 18. Therefore, the magnetization direction of free magnetic layer VL does not change when the data write magnetic fields applied thereto have intensities corresponding to a region inside the asteroid characteristic line.
As can be seen from the asteroid characteristic line, the magnetization threshold required for changing the magnetization direction along the easy axis can be lowered by applying the magnetic field in the direction of the hard axis to free magnetic layer VL.
When the operation point in the data write operation is designed, for example, as shown in FIG. 18, the data write magnetic field in the MTJ cell selected as a data write target is designed such that the data write magnetic field in the direction of the easy axis has an intensity of HWR. Thus, the data write current flowing through bit line BL or write digit line WDL is designed to take a value, which can provide the data write magnetic field of HWR. In general, data write magnetic field HWR is represented by a sum of a switching magnetic field HSW required for switching the magnetization direction and a margin xcex94H. Thus, it is represented by an expression of HWR=HSW+xcex94H.
For rewriting the storage data of the MTJ memory cell, i.e., the magnetization direction of tunneling magneto-resistance element TMR, it is necessary to pass the data write currents at a predetermined level or higher through write digit line WDL and bit line BL. Thereby, free magnetic layer VL in tunneling magneto-resistance element TMR is magnetized in the same parallel direction as fixed magnetic layer FL or untiparallel direction in accordance with the direction of the data write magnetic field along the easy axis (EA). The magnetization direction, which was once written into tunneling magneto-resistance element TMR, and thus the storage data of MTJ memory cell is held nonvolatilely until next data writing is executed.
FIG. 19 conceptually shows an operation of reading data from the MTJ memory cell.
Referring to FIG. 19, access transistor ATR is turned on in response to activation of word line WL in the data read operation. Write bit line WBL carries ground voltage GND. Thereby, tunneling magneto-resistance element TMR is electrically coupled to read bit line RBL while being pulled down with ground voltage GND.
In this state, read bit line RBL is pulled up with a predetermined voltage, whereby a current path including read bit line RBL and tunneling magneto-resistance element TMR carries a memory cell current Icell corresponding to storage data of the MTJ memory cell. For example, this memory cell current Icell is compared with a predetermined reference current, whereby storage data can be read out from the MTJ memory cell.
As described above, the electric resistance of tunneling magneto-resistance element TMR is variable in accordance with the magnetization direction, which is rewritable by the data write magnetic field applied thereto. Therefore, nonvolatile data storage can be executed by establishing a correlation of electric resistances Rmax of Rmin of tunneling magneto-resistance element TMR with respect to levels (xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d) of the storage data.
As described above, the MRAM device executes the data storage by utilizing a difference xcex94R (=Rmaxxe2x88x92Rmin) in junction resistance corresponding to a difference between storage data levels of tunneling magneto-resistance element TMR. However, this resistance difference xcex94R is not sufficiently large in a general MTJ memory cell. Typically, electric resistance Rmin is equal to tens of percent of Rmax. Therefore, memory cell current Icell does not change significantly in accordance with the storage data level, but changes only on the order of microamperes (xcexcA: 10xe2x88x926A).
Accordingly, it is required to make a current comparison between the passing currents of the selected memory cell with high precision. If only a current mirror sense amplifier having a general structure is used for such current comparison, the current difference cannot be detected with sufficient precision, and a malfunction may occur.
An object of the invention is to provide a semiconductor memory device, which can execute data reading based on a current comparison or a voltage comparison made with high precision.
A semiconductor memory device according to the invention includes a plurality of memory cells each having passing current changing in accordance with storage data during access; an access current transmitting circuit for passing, to a first node, an access current corresponding to the passing current of a selected memory cell selected from the plurality of memory cells as an access target; a reference current generating circuit for passing a reference current to a second node during data reading; a current comparing circuit for producing a read voltage corresponding to a difference between currents flowing through the first and second nodes, respectively; a test current supply circuit for supplying an externally test current to at least one of the first and second nodes in a test mode.
Preferably, the semiconductor memory device further includes an offset detecting circuit for evaluating offset occurring in the current comparing circuit based on the read voltage in the test mode. The test current supply circuit supplies the test currents to each of the first and second nodes in the test mode.
The semiconductor memory device thus constructed includes the test mode for evaluating the offset based on results of a comparison, which is made with the same current by the current comparing circuit extracting a current difference between the passing current of the selected memory cell and the reference current. Therefore, the offset of the current comparing circuit can be tuned with high precision. As a result, accurate data reading can be executed by detecting a minute current difference.
Preferably, the semiconductor memory device further includes a current detecting circuit for detecting a relationship in magnitude of one of the access current and the reference current with the test current based on the read voltage in the test mode. The test current supply circuit supplies the test currents to one of the first and second nodes, instead of one of the access current and the reference current, in the test mode.
In the semiconductor memory device described above, the passing current of the selected memory cell and the reference current can be determined by individually detecting the relationship in magnitude with respect to the externally test current.
According to another aspect of the invention, a semiconductor memory device includes a plurality of memory cells each for holding storage data; a first node, in a read operation, being electrically connected to a selected memory cell selected from the plurality of memory cells as an access target; a second node for transmitting a electric reference signal in order to be compared with a electric signal transmitted by the first node, in the read operation; a data read circuit for outputting a read voltage according to a difference between the electric signals of the first and second nodes in the data read operation; and an offset tuning circuit for tuning input impedance of the first and second nodes in accordance with first and second control voltages obtained by feedback of the read voltage so as to keep the read voltage within a predetermined range when the data read operation is inactive.
Preferably, The data read circuit outputs the read voltage corresponding to a voltage difference between the first and second nodes in the data read operation. The semiconductor memory device further includes a voltage holding circuit for holding the first and second control voltages; and a switch circuit for interrupting a feedback path of the read voltage in the data read operation.
In the semiconductor memory device described above, the offset tuning of the data read circuit, which performs the data reading in accordance with a voltage comparison, can be automatically executed when the data read operation is inactive. Therefore, the data read operation can be executed with the offset kept in the tuned state so that the data read operation can be performed rapidly and precisely.
Preferably, each of the plurality of memory cells has passing current changing in accordance with the storage data during access. The semiconductor memory device further includes an access current transmitting circuit for passing, to the first node, an access current corresponding to the passing current of the selected memory cell; a reference current generating circuit for passing a reference current to the second node as the electric reference signal in the data read operation; and a current switching circuit for carrying the reference current instead of the access current to the first node when the data read operation is inactive. The data write circuit outputs the read voltage according to a difference between currents flowing through the first and second nodes, respectively.
Preferably, the semiconductor memory device further includes a voltage holding circuit for holding the first and second control voltages, and a switch circuit for interrupting a feedback path of the read voltage in the data read operation.
In the semiconductor memory device described above, the offset tuning of the data read circuit, which performs the data reading in accordance with a current comparison, can be automatically executed when the data read operation is inactive. Therefore, the data read operation can be executed with the offset kept in the tuned state so that the data read operation can be performed rapidly and precisely.
According to further another aspect of the invention, a semiconductor memory device includes a plurality of memory cells having passing currents changing in accordance with storage data during access; an access current transmitting circuit for passing an access current depending on the passing current to a first node, based on a comparison between a reference voltage and a voltage on an internal node passing the passing current therethrough and connected to the selected memory cell selected as an access target from the plurality of memory cells; a reference current generating circuit for passing a reference current to a second node during data reading; a current comparing circuit for producing a read voltage corresponding to a difference between the currents flowing through the first and second nodes, respectively; and a reference current tuning circuit for tuning a level of the reference voltage in accordance with a result of manufacturing of each memory cell.
According to the semiconductor memory device described above, the level of the reference voltage used in the current transmitting circuit can be controlled in accordance with the results of manufacturing of the memory cell. Therefore, the access current according to the passing current of the selected memory cell can be detected while holding constant characteristics in the current transmitting circuit by following variations due to manufacturing of the memory cells.
According to a further aspect of the invention, a semiconductor memory device includes a plurality of memory cells, an access current transmitting circuit, a reference current generating circuit and a current comparing circuit. In the plurality of memory cells, passing currents change in accordance with storage data during access. The access current transmitting circuit passes through a first node an access current corresponding to the passing current of the selected memory cell selected as an access target from the plurality of memory cells. The reference current generating circuit passes a reference current through a second node during data reading. The reference current generating circuit includes a plurality of dummy memory cells formed on the semiconductor memory device, and each having a structure similar to that of the memory cell, and a current generating circuit for generating the reference current based on the passing currents of the plurality of dummy memory cells. At least one of the plurality of dummy memory cells store one of two kinds of levels of the storage data, and at least another the memory cells store the other of the two kinds of levels of the storage data. The current comparing circuit produces a read voltage corresponding to a difference between currents flowing through the first and second nodes, respectively.
According to the semiconductor memory device described above, the level of the reference voltage used in the current transmitting circuit can be tuned in accordance with an actual electric resistance of the memory cell. Accordingly, the characteristics of the current transmitting circuit can be kept constant while following variations due to manufacturing of the memory cells.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.